The present invention relates in general to semiconductor devices and their fabrication. More specifically, the present invention relates to a co-integrated fabrication processes and resulting structures for forming standard-gate and extended-gate nanosheet/nanowire transistors on the same substrate.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as silicon channel n-type field effect transistors (nFETs) and silicon germanium channel p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as nanosheet (or nanowire) transistors, can provide increased device density and increased performance over planar transistors. Nanosheet transistors, in contrast to conventional planar FETs, include a gate stack that wraps around the full perimeter of multiple nanosheet channel regions for improved control of channel current flow. Nanosheet transistor configurations enable fuller depletion in the nanosheet channel regions and reduce short-channel effects. In order to increase the maximum gate voltage of certain transistors, so-called extended gate (EG) nanosheet transistors have been developed that include a larger volume of gate metal and/or a thicker gate oxide than so-called standard-gate (SG) nanosheet transistors.